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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:38:35 03/03/2012 
-- Design Name: 
-- Module Name:    Acc - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Acc is
    Port ( alu_o : in  STD_LOGIC_VECTOR (7 downto 0);
           acc_o : out  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
           load_acc_en : in  STD_LOGIC);
end Acc;

architecture Behavioral of Acc is
begin
	process(clk)
	begin
		if (rising_edge(clk) and load_acc_en = '1') then
			acc_o <= alu_o;
		end if;
	end process;
end Behavioral;

